Low Power Techniques for Digital System Design

Low Power Design Techniques for Digital Logic Circuits

With the rapid increase in the density and the size of chips and systems, area and power dissipation become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power design techniques are essential for today's VLSI industry. The history of symbolic logic and some typical techniques for finite state machine (FSM) logic synthesis are reviewed. The state assignment is used t...

Low Power Techniques for Digital GaAs VLSI

This paper presents a survey of low-power digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems and proposes new design concepts in methodology and architecture based on implementation of Pseudo-Dynamic Latched Logic in order to achieve reasonable power-delay-area tradeoff The approach is highly suitable for self-timed systems where the complexities of clock sk...

Low Power Design Techniques

The demand for portable electronic devices that offer greater functionality and performance at lower costs and smaller sizes has increased rapidly. This market trend is driving the need for efficient System-on-Chip (SoC) designs, where the power arises as the one of the biggest problems. The microprocessor design has traditionally focused on dynamic power (active power) consumption as the limit...

Low power system design techniques for mobile computers

Portable products such as pagers, cordless and digital cellular telephones, personal audio equipment, and laptop computers are being used increasingly. Because these applications are battery powered, reducing power consumption is vital. In this report we first give the properties of low power design and techniques to exploit them on the hardware level such as: minimize capacitance, avoid wastef...

Emerging Power-Gating Techniques for Low Power Digital Circuits